There is a demand for a reduction in power to be consumed by a circuit system including a logic circuit such as a processor and a memory and a reduction in power to be consumed by a semiconductor device (semiconductor circuit or LSI) provided with the circuit system. Various methods for reducing power to be consumed have been proposed. One of the methods is to stop supply of operating power to a part that does not operate. In this method, when a logic circuit such as a processor does not operate, supply of operating power to the logic circuit is stopped. When the memory does not operate, input and output of data to and from the memory are stopped, and the memory may hold stored data or may not hold the stored data. If the memory does not hold the stored data, supply of operating power is stopped so as to reduce power to be consumed. If the memory holds the stored data, a substrate voltage Vbb (described later) is applied, for example.
Various methods for reducing power to be consumed while achieving requested performance (operating speed) in an operating circuit system have been proposed as well as the aforementioned method for stopping supply of operating power to a part that does not operate. A method for dynamically changing an operating speed (clock frequency) and an operating power supply voltage on the basis of a loaded state of the circuit system so as to reduce power to be consumed has been proposed. In the embodiments described later, an operating speed is a fixed value. The embodiments, however, are applicable to the case where the operating speed is dynamically changed.
Power to be consumed by a semiconductor device (semiconductor circuit) and performance (operating speed) of the semiconductor device depend on a voltage Vdd (hereinafter referred to as operating voltage) of an operating power supply and a transistor threshold voltage Vth. For example, when the operating voltage Vdd is reduced, switching power may be reduced in proportion to the square of the operating voltage Vdd. The reduction in the operating voltage Vdd, however, may cause a reduction of the performance. In order to maintain the performance upon the reduction in the operating voltage Vdd, there is a method for reducing the transistor threshold voltage Vth by controlling a voltage Vbb (hereinafter referred to as substrate voltage) of a substrate power supply. When the transistor threshold voltage Vth is reduced, a sub-threshold leakage current of a transistor increases. The relationship between power to be consumed by the semiconductor circuit and the performance of the semiconductor circuit is a tradeoff relationship. Thus, how to reduce power to be consumed is a problem. Various methods for controlling the voltages Vdd and Vbb on the basis of an operational state of the semiconductor circuit and reducing power to be consumed by the semiconductor circuit have been proposed.
For example, the semiconductor circuit is in an active (operating) state or a standby (sleep) state. In the active state, the semiconductor circuit executes a process. In the standby state, the semiconductor circuit does not execute a process. There is a method for reducing a leakage current in the standby state by reducing an operational frequency (clock frequency), applying the substrate voltage Vbb, and reducing the voltage Vdd in order to cause the semiconductor circuit to become the standby state. Power to be consumed by the semiconductor circuit mainly includes switching power and leakage power. In the active state, the semiconductor circuit operates at an operational frequency for execution of a requested process and the switching power is dominant. In the standby state in which a process is almost not executed, the leakage power is dominant. Thus, in the standby state, it is effective to reduce the leakage power even if a speed of the circuit is sacrificed. In this method, even if the speed of the circuit is reduced, the operational frequency is reduced, an erroneous operation is not executed, and the leakage power is reduced by highly applying the substrate voltage Vbb and reducing the operating voltage Vdd.
Another method is known, which is to block supply of power to the logic circuit in a standby state and apply the voltage Vbb to an SRAM in order to reduce the amount of a leakage current in a semiconductor circuit (LSI) that has the logic circuit and the SRAM. In addition, the following method has been proposed, which is to block supply of power to a region that is among blocks obtained by dividing the SRAM and in which data is not held in the standby state. This method is to reduce leakage power of the standby state. Leakage power is reduced by blocking supply of power to a circuit that does not operate in the standby state. For the SRAM that holds data in the standby state, leakage power is reduced by applying the voltage Vbb.
As described above, leakage power is reduced by stopping supply of power to a logic circuit such as a processor and a memory block that is not used. For the logic circuit such as a processor, a method has been proposed, which is to stop power supply when the logic circuit is not used, set an operating frequency on the basis of a requested processing speed upon an operation, set an operating voltage and a substrate voltage in consideration of a temperature when the logic circuit operates. For the memory that holds data even in the standby state, the leakage power is reduced by controlling the voltage Vbb.
Japanese National Publication of International Patent Application No. 2010-519612, Japanese Laid-open Patent Publications Nos. 2003-132683, 2000-149561, 09-212416, and 04-329663 and Japanese Patent No. 4835856 are examples of related art.